Implementation and Performance Analysis of different Multipliers
Multipliers are very important and are used in various applications. This paper presents analysis of different multipliers design such as array multiplier, row bypassing multiplier and column bypassing multiplier. The multipliers are implemented using verilog HDL and the simulation is done in Modelsim simulator. The multipliers are compared in terms of delay and area. It is observed that delay in column bypassing multiplier is 22.48% less than array multiplier and 21.25% less than row bypassing multiplier. It is also observed that the column bypassing multiplier has less area than araay multiplier and row bypassing multiplier.
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