Design and Implementation of a Low Power and Area Efficient Sequential Multiplier

  • Mohit Kumar Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India
  • Subhash Chandra Yadav Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India
Keywords: Shift and add multiplier, Controller, Power consumption, Area, Xilinx

Abstract

A multiplier plays a major role in various digital systems. The area, speed and power consumption of any digital system, which has a multiplier as its component, depend upon the hardware used for the multiplier. In this paper we proposed a sequential multiplier which has a lower area requirement and lower power consumption in comparison of the conventional sequential multiplier. We can use the proposed system where long battery life is required and/or reduced hardware is required. The speed of the proposed multiplier is a little bit slower than the conventional one. So we can use the proposed system where long battery life is required and speed is not the major requirement.

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Author Biographies

Mohit Kumar, Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India

Mohit Kumar completed his Bachelor in Technology at IIMT Engineering College, Meerut, India. He is pursuing Master in Technology in VLSI Design and System at Graphic Era Deemed University, Dehradun, India. His areas of interest include Digital Design and FPGA Implementation.

Subhash Chandra Yadav, Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India

Mr. Subhash Chandra Yadav is Assistant Professor in Graphic Era University Dehradun, India. He completed his M.Tech. Degree from Kurukshetra University, Kurukshetra, India. His area of interest includes VLSI Design, Logic Design and Signal Processing.

References

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Published
2016-03-18
Section
Articles