Design of 16X16 SRAM Array Using 7T SRAM Cell for Low Power Applications
Static Random Access Memory (SRAM) plays a vital role in various applications like cache memories, microprocessors and portable devices. As the technology’s node scaling down, leakage power is the major problem in SRAM cell concerned for the low power applications. So, there is a requirement of low power adequate memory design. The main goal of this paper is to design a low power 16X16 SRAM array using 7T SRAM cell. The proposed architecture of 16X16 SRAM array is similar to 16X16 SRAM array using conventional 6T SRAM cell, only one additional NMOS transistor is placed between pull down transistors and ground node. This architecture reduces static power in standby mode. Cadence (version 6.1.5) simulation tool is used for designing. Comparative analysis is performed in terms of total power consumption. Peripheral components of complete 16X16 SRAM array has been designed such as SRAM cell, write driver circuit, precharge circuit, row /column decoder and sense amplifier. For noise reduction during read operation, Differential type sense amplifier is used that has the ability of common mode noise voltage rejection. Power Consumption of 16X16 SRAM array using 7T SRAM cell is 20.04mW is measured that is 18.4% less compared to 16X16 SRAM array using 6T SRAM array. Transient analysis of write and read operations for both logic -0 and logic -1 is performed. For designing standard GPDK(generic process design kit) 180nm library is used.
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