Design of 16X16 SRAM Array Using 7T SRAM Cell for Low Power Applications

  • Rashmi Bisht Department of Electronics and Communication Engineering, Graphic Era University, Dehradun, India
  • Ashutosh Pranav Department of Electronics and Communication Engineering, Graphic Era University, Dehradun, India
Keywords: SRAM, WE, WL, SE


Static Random Access Memory (SRAM) plays a vital role in various applications like cache memories, microprocessors and portable devices. As the technology’s node scaling down, leakage power is the major problem in SRAM cell concerned for the low power applications. So, there is a requirement of low power adequate memory design. The main goal of this paper is to design a low power 16X16 SRAM array using 7T SRAM cell. The proposed architecture of 16X16 SRAM array is similar to 16X16 SRAM array using conventional 6T SRAM cell, only one additional NMOS transistor is placed between pull down transistors and ground node. This architecture reduces static power in standby mode. Cadence (version 6.1.5) simulation tool is used for designing. Comparative analysis is performed in terms of total power consumption. Peripheral components of complete 16X16 SRAM array has been designed such as SRAM cell, write driver circuit, precharge circuit, row /column decoder and sense amplifier. For noise reduction during read operation, Differential type sense amplifier is used that has the ability of common mode noise voltage rejection. Power Consumption of 16X16 SRAM array using 7T SRAM cell is 20.04mW is measured that is 18.4% less compared to 16X16 SRAM array using 6T SRAM array. Transient analysis of write and read operations for both logic -0 and logic -1 is performed. For designing standard GPDK(generic process design kit) 180nm library is used.


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Bellerimath, P. S., & Banakar, R. M. (2013). Implementation of 16X16 SRAM memory array using 180nm technology. International Journal of Current Engineering and Technology, Special Issue, 288-292.

Ho, D., Iniewski, K., Kasnavi, S., Ivanovi, A., & Natarajan, S. (2006). Ultra low power 90nm SRAM cell for wireless sensor network applications. IEEE Symposium on Circuits and Systems, 4131-4134.

Kang, S. M., & Leblibici, Y. (2003). CMOS (Third edition). Tata McGraw Hill.Kiran, P. V., & Saxena, N. (2015, February). Design and analysis of different types SRAM cell topologies. In Electronics and Communication Systems (ICECS), 2015 2nd International Conference on (pp. 1060-1065). IEEE.

Mishra, M., Majumdar, S., Malviya, D.,& Bansod, P. P. (2012). Design of SRAM cell in 0.18μm technology. International Conference on Information Communication and Embedded Systems, 457-463.

Mohammad, B., Dadabhoy, P., Lin, K., & Bassett, P. (2012, December). Comparative study of current mode and voltage mode sense amplifier used for 28nm SRAM. In 2012 24th International Conference on Microelectronics (ICM) (pp. 1-6). IEEE.

Seevinck, E., List, F. J., & Lohstroh, J. (1987). Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits, 22(5), 748-754.

Shah, K. C., Gandhi, D. N., & Nagpara, B. H.(2013). Design and analysis of 256 bit SRAM in deep submicron CMOS technologies. Journal of Information, Knowledge and Research in Electronics and Communication Engineering, 2(2), 812-817.

Shah, R. K., Hussain, I.,& Kumar, M. (2015). Performance comparison for different configurations of SRAM cells. International Journal of Innovative Research in Science, Engineering and Technology, 4(1), 18543-18545.

Shukla, N. K., Singh, R. K., & Pattanaik, M. (2011).Design and analysis of a novel low power SRAM bit-cell structure at deep sub micron CMOS technology for mobile multimedia applications. International Journal of Advanced Computer Science and Applications, 2(5), 43-49.